Multi-component electronic signal processing systems typically contain a number of modules that are respectively dedicated to the performance of individual signal processing functions. This is particularly true in opto-electronic devices, such as hybrid infrared imaging systems, in which both high resolution and compact physical size are obtained by integrating a plurality of photoresponsive elements (for example, a two dimensional focal plane array of HgCdTe photodiodes) within their own dedicated semiconductor wafer, and housing the associated signal processing electronics in a separate module. This separate unit containing the signal processing electronics typically takes the form of a large scale integrated circuit chip, from one planar surface of which there extends a plurality of land regions or metallic bumps as the interconnect mechanism to be joined with corresponding signal coupling regions on the rear (non-imaging surface) of the photodiode wafer.
As the optical density of focal plane arrays increases, the ability to house the signal processing components within associated, limited area, regions of an adjacent `piggy-back` semiconductor wafer becomes increasingly difficult. Namely, as the number of interconnect bumps required to accommodate the smaller sized (and more closely spaced) photodiodes increases, the amount of semiconductor real estate that is available within the `piggy-back` substrate for the device regions of the signal processing components diminishes, and eventually limits the resolution of the array for a given imaging size.
One proposal to obviate this area limitation is diagrammatically depicted in FIG. 1 and involves installing a photodiode die or strip 11 within a slot 13 in one end 15 of a ceramic printed circuit board 21, and housing its associated signal processing electronics in the remainder of the printed circuit board. Multiple circuit boards are then stacked in a parallel, layered arrangement, as shown in FIG. 2, so that the ends of adjacent circuit boards, in which the photodiode strips are mounted, form a focal plane array 25. Since, theoretically, the adjacent, parallel-disposed printed circuit boards may be of any length L, the number of signal processing devices they are to accommodate is not limited, as in the case of a conventional back-to-back configuration. In this parallel printed circuit board approach, each ceramic printed circuit board, the thickness T of which is typically on the order of 20 mils, contains multiple pockets 27 into which the signal processing chips 29 are inserted, the chips being interconnected by conventional wiring layers 31 that extend over the surface of the board among the signal processing chips and the photo elements of the die strip at the end of the board. Because of the substantial thickness of each board (e.g. 20 mils) and the resultant spacing between photodiode die strips of adjacent boards, not only is the focal plane array resolution-limited, but there is a `dead space` (occupied by the material of the printed circuit board) between adjacent end slot-captured photodiode strips, requiring a complicated scanning and interpolation algorithm in the course of driving and processing the outputs of the photodiodes. Moreover, the overall size of a 128.times.128 array requires a unit approximately four inches on an edge, so that its overall size is not insubstantial.